Due to the increased demand for quickly transferring growing amounts of data, there has been a rapid spread in transmission networks handling digital data in recent years. In such transmission networks, source information is coded at a source node in synchronization with a system clock and transmitted as digital data through the transmission network to a receiver node. The receiver node uses its receiver clock for decoding the received digital data to reproduce the original source information.
In a mesochronous transmission network (e.g., a High Definition Multimedia Interface, referred to as HDMI), the reference clocks for the transmitter and for the receiver operate at the same frequency, however do not have a phase relation. In order to correctly recover the data, the receiver must sample the data exactly at an incoming data eye.
In a plesiochronous transmission network (e.g., M-Phy or USB), the reference clocks for the transmitter and for the receiver operate at slightly different frequencies. Thus, in these networks, the requirement for placing a strobe at an incoming data eye of the received data further encompasses a correction of the frequency variation. Fulfilling these requirements is challenging in the light of reducing the needed hardware of such receiver devices.
Although the frequency of the clock signal may be coordinated between a transmitter and a receiver prior to the transmission of data, the received digital data signal may still show temporal variations in consecutive edges of the data signal, also referred to as jitter. Jitter, which may also be characterized as short-term variations of a signal with respect to its ideal position in time, may negatively impact data transmission quality. Jitter may be induced and coupled onto a clock signal from several different sources and is not uniform over all frequencies. In digital systems, jitter may also lead to a violation of timing margins, causing circuits to behave improperly.
Jitter may be caused by attenuation characteristics of a channel, cross talk, reflection or electromagnetic interference (EMI) from nearby devices and equipment, random thermal noise from a crystal, or due to the fact that crystals of the receiver's clock and transmitter's clock are slightly different in most cases.
That is, the clock recovery circuit needs to have a sufficient high-frequency jitter tolerance. If the these temporal variations in consecutive edges of the data signal are not compensated, errors will occur in determining the received data.
The transmission of data at high data rates increasingly depends on the performance of clock data recovery (CDR) that is used to recover the transmitted data signal from the received signal. High performance CDR methods are essential to accurately extract timing information from high-frequency signals and to recover the transmitted data signal from the received signal upon retrieving the correct clock from the received data stream.
In case of, for instance, the deviation of the frequency between a receiver clock and the transmitter clock of the data stream exceeding a certain threshold, data may be lost due to the correct detection of the data bits being impossible.
Several techniques have been proposed that provide clock data recovery, even in case of jitter. One known technique is over-sampling clock data recovery (CDR), which over-samples the incoming digital data and chooses which sample of the over-sampled data best represents the data. In particular, a bit of the incoming data stream is sampled at plural strobes. Then, the strobes at the transition points of the bit determine the edge(s) of the bit. Based on the strobes at the edge(s) of the bit, the middle strobe, which represents the clock, is determined by selecting the strobe being farthest from the edge(s). However, employing this technique leads to an increase in hardware and current consumption due to more numbers of samples being required for finding the edge(s) of a bit, in case the jitter increases.
According to a further drawback of this technique, in case of frequency drift between transmitter clock and receiver clock, an extra elasticity buffer is required for preventing data loss, wherein the elasticity buffer is proportional to the maximum data processed at a time.
A different approach relating to clock data recovery is known as the Bang-Bang Phase Detector based CDR. For each data bit, samples are taken by phase-shifted clock signals. It is sensed whether an input data edge is before or after a corresponding clock edge, and then a positive or negative pulse is output, respectively. In cases of no data transition being close to a clock edge, the phase detector maintains an output of zero. Further, the Bang-Bang Phase Detector merely distinguishes the sign of a phase error, however not its magnitude.
As a further drawback of known CDR techniques, more than three strobes are required for sampling the eye-opening. Accordingly, this results in the requirement of an increased number of clock phases, wherein the increased number of needed strobes is unsuitable for high performance CDR applications in high speed networks.
Another example of a circuit for clock data recovery is disclosed in H. Lee, et al, “A 5 Gb/s 0.25 μm CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit”, IEEE Journal of Solid-State Circuits; Vol. 37; No. 12; December 2002. Therein, a clock/data recovery circuit incorporating a variable-interval 3x-oversampling method is described for enhanced high-frequency jitter tolerance. The CDR circuit traces the eye-opening region to place the data-sampling clock exactly at the center of a data eye, responding to the shape and magnitude of jitter. Each data bit is sampled by three strobes. After analyzing these samples, the PLL frequency is adapted. The CDR operates at a data rate of 5 Gb/s and shows a bit error rate of less than 10-13 when the magnitude of data jitter reaches 60.5% of a bit time. However, the lock time of the circuit is very high and any frequency drift will result in a repeatedly performed adaptation of the PLL frequency. Furthermore, there may also be a limitation of the PLL track bandwidth.
However, the aforementioned proposed techniques could not provide a satisfactory method and apparatus for clock recovery in high speed networks in case of the occurrence of high frequency jitter and high frequency drift.
Given these problems with the existing technology, it would be advantageous to provide an improved method which allows recovering the clock of a received data stream, even in case of high jitter and high frequency drift. Moreover, it would be advantageous to provide an improved apparatus being capable of performing the method for recovery of a clock from a received digital data stream.